1. Field of the Invention
The present invention relates to an electronic circuit technology, more specifically, to a data transmission system using a pair of complementary signals as an edge-aligned strobe signal and input/output buffers therein.
2. Description of the Prior Art
Conventional high-speed input/output buses employ a pseudo-differential scheme or a fully differential scheme to restore small swing signals back to full swing of logic “1” or “0.” These data will be latched by synchronous clocks or strobe signals sent from the transmitter. The difference between the pseudo-differential data comparator and the fully differential data comparator is described as follows.
FIGS. 1A and 1B (Prior Art) are a circuit diagram and a timing diagram of the conventional pseudo-differential data comparator, respectively. As shown in the figures, the pseudo-differential data comparator 10 receives a data signal (DATA) and a reference voltage (VREF). The logic level of the data signal (DATA) is determined by comparing the data signal (DATA) with the reference voltage (VREF) and then generates the output signal (DOUT). On the other hand, FIGS. 2A and 2B are a circuit diagram and a timing diagram of the conventional fully differential data comparator, respectively, which is different from the conventional pseudo-differential data comparator in their received signals. The conventional fully differential data comparator receives a non-inverting data signal (DATA) and its inverse signal (DATA#), which constitute a differential signal. The output signal (DOUT) is determined by comparing the non-inverting data signal (DATA) and the inverting data signal (DATA#).
However, both of the conventional data comparators still suffer from some drawbacks. In the pseudo-differential scheme, the slew rate of the data signal (DATA) and the variation of the reference voltage (VREF) will affect the output timing of the output signal (DOUT), which is unfavorable to the applications of high-speed I/O buses. In the fully differential scheme, every data signal requires two pins to send the original and its inverse signal, which can cause a limitation in current chip design where the die size and the substrate ball-out are restricted.
In addition, when the data signal is transmitted to the receiver through the transmission line, a skew may occur due to various environmental factors, such as simultaneous switching output (SSO) effect, signal coupling, crosstalk, multiple routing paths and power/ground noises. Accordingly, data sampling is liable to be erroneous if the skew is larger.